Integrated circuit memory devices are widely used in consumer and commercial electronics. It is generally desirable to increase the speed of integrated circuit memory devices. Speed may be increased by reducing the delays in read and write operations of the memory devices. For example, the delay in activating a word line in response to address signals may be reduced. This delay may be caused by standby time that is used to activate components after a control signal is applied, transmission delays at each buffer or gate, and precharging times.
FIG. 1 is a block diagram of a conventional row address decoder. The delays that are produced in the row address decoder will be described with reference to FIG. 1.
In FIG. 1, address buffers 10a and 10b receive external input signals Ai and Aj of a TTL level and convert the level of the received signals to a CMOS level, to thereby generate the converted signals as address signals PAi and PAj. A row address latch 12 receives the address signals PAi and PAj and latches the received address signals in accordance with an internal clock PCLK and an activation command PRA to generate the latched address signals as effective addresses RAij. A predecoder 14 predecodes the effective addresses RAij and generates predecoded addresses DRAij. A main decoder 16, which may be present for each bank in the memory device, receives the predecoded addresses DRAij, and main-decodes and sufficiently boosts such signal to drive a word line at the boosted voltages WLij.
FIG. 2 is a timing diagram showing a timing relationship of signals of FIG. 1 during operation of the address decoder.
When a row active command ACTIVE is asserted, the level of the external signals Ai and Aj is shifted to a CMOS level by the address buffers 10a and 10b, and then latched in response to the internal clock PCLK and the activation command PRA. After the latched address signals are output as the effective addresses RAij, the predecoder 14 is enabled in response to an enable signal PDRAE to generate the predecoded addresses DRAij. When a precharge command PRECHARGE is asserted, the decoded addresses DRAij is reset by a predecoder reset signal PDRAP and the decoder returns to a precharge state.
As shown in FIG. 2, even after the decoded addresses DRAij are output, the effective addresses RAij maintains the previous state until a next activation command PRA is input. Accordingly, the predecoder 14 should not be enabled until new effective addresses RAij are generated since the previous effective addresses RAij are applied to the predecoder 14 until the new effective addresses RAij are generated. If the predecoder 14 is enabled before the new effective addresses RAij are generated, the new effective addresses RAij may not be applied to the predecoder 14, so that a wrong word line may be selected.
As described above, since the predecoder 14 should not be enabled until the new effective addresses RAij are generated, there should be a sufficient standby time before the predecoder enable signal PDRAE is asserted to enable the predecoder after the effective addresses RAij are generated. This may be an obstacle in increasing the speed of the memory device.